The invention relates to correcting misaligned memory accesses.
Computer systems generally include one or more Peripheral Component Interface (PCI) buses that provide a special communication protocol between peripheral components, such as video controllers and network interface cards, and the computer system's main memory. When system memory and the peripheral components (PCI devices) reside on different buses, a bridge is required to manage the flow of data transactions between the two buses. PCI bus architecture is defined by the PCI Local Bus Specification, Revision 2.1 ("PCI Spec 2.1"), published in June 1995, by the PCI Special Interest Group, Portland, Oreg., incorporated by reference. PCI-to-PCI bridge architecture is defined by the PCI-to-PCI Bridge Architecture Specification, Revision 1.0 ("PCI Bridge Spec 1.0"), published in April 1994, by the PCI Special Interests Group, incorporated by reference.
Among the types of transactions that may be maintained by PCI devices are memory reads. Such read cycles, which under the PCI Spec 2.1 and the PCI Bridge Spec 1.0 architectures can be delayed transactions (i.e., they complete on the target bus before they complete on the initiating bus), include Memory Read (MR) transactions, which involve transfers of individual dword of data, Memory Read Line (MRL) transactions, which involve transfer of one entire cache line (eight dwords), and Memory Read Multiple (MRM) transactions, which involve transfers of eight cache lines of data. A Memory Read transaction involving multiple dwords of data takes longer to complete on the CPU host bus than either a Memory Read Line or Memory Read Multiple transaction because, in a MR transaction, the inherent host bus latency is experienced each time a word of data is transferred. This latency is experienced only once during a MRM transaction and only once per cache line during a MRL transaction. However, when either a MRL or MRM memory access does not begin at a cache line boundary (i.e., when the MRL or MRM transaction is "misaligned"), the transaction must be treated as a MR cycle, with a single word of data transferred at a time, until the first cache line boundary is reached.